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1 2002 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5903/6 ? idt72v71623 3.3 volt time slot interchange digital switch with rate matching 2,048 x 2,048 may 2002 idt and the idt logo are registered trademarks of integrated device technology, inc. the st-bus ? is a trademark of mitel corp. output mux receive serial data streams rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 ode f0i vcc cs ds r/ w a0-a13 gnd dta 5903 drw01 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 loopback test port data memory internal registers microprocessor interface timing unit tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 tx8 tx9 tx10 tx11 tx12 tx13 tx14 tx15 clk fe/ hclk wfps tdi tms tck tdo trst reset oei0 oei1 oei2 oei3 oei4 oei5 oei6 oei7 oei8 oei9 oei10 oei11 oei12 oei13 oei14 oei15 connection memory transmit serial data streams d0-d15 functional block diagram features: ? ? ? ? ? up to 16 serial input and output streams ? ? ? ? ? maximum 2,048 x 2,048 channel non-blocking switching ? ? ? ? ? accepts data streams at 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s ? ? ? ? ? rate matching capability: mux/demux mode ? ? ? ? ? output enable indication pins provided by dedicated pins ? ? ? ? ? per-channel variable delay mode for low-latency applications ? ? ? ? ? per-channel constant delay mode for frame integrity applica- tions ? ? ? ? ? automatic identification of st-bus ? and gci serial streams ? ? ? ? ? automatic frame offset delay measurement ? ? ? ? ? per-stream frame delay offset programming ? ? ? ? ? per-channel high-impedance output control ? ? ? ? ? per-channel processor mode to allow microprocessor writes to tx streams ? ? ? ? ? direct microprocessor access to all internal memories ? ? ? ? ? memory block programming for quick setup ? ? ? ? ? ieee-1149.1 (jtag) test port ? ? ? ? ? internal loopback for testing ? ? ? ? ? available in 144-pin thin quad flatpack (tqfp) and 144-pin ball grid array (bga) packages ? ? ? ? ? operating temperature range -40 c to +85 c ? ? ? ? ? 3.3v i/o with 5v tolerant inputs and ttl compatible outputs description: the idt72v71623 has a maximum non-blocking switch capacity of 2,048 x 2,048 channels with data rates at 2.048 mb/s, 4.096 mb/s, 8.192 mb/s or 16.384 mb/s. with 16 inputs and 16 outputs, a variety of rate combinations is supported under mux/demux mode, to allow for switching between streams of different data rates.
2 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 pin configurations rx0 rx1 rx3 rx6 tx1 tx4 tx7 rx10 rx12 rx15 tx10 tx11 clk ode rx2 rx5 tx0 tx3 tx6 rx9 rx13 rx14 tx9 tx12 f0i fe/hclk reset rx4 rx7 tx2 tx5 rx8 rx11 tx8 tx13 tx14 tms wfps tdi vcc vcc vcc vcc vcc vcc tx15 ic ic td0 tck trst vcc ic ic ic ds cs r/ w vcc ic ic ic a0 a1 a2 vcc oei0 oei1 oei2 a3 a4 a5 a13 oei3 oei4 oei5 a6 a7 a8 d15 oei6 ic oei7 a9 a10 dta d9 d6 d3 d0 oei13 oei10 ic ic ic a11 ic d12 d11 d7 d4 d1 oei14 oei11 oei8 ic ic a12 d14 d13 d10 d8 d5 d2 oei15 oei12 oei9 ic ic a1 ball pad corner a b c d e f g h j k l m 123456789101112 5903 drw02 gnd gnd gnd gnd vcc gnd gnd gnd gnd vcc vcc gnd gnd gnd gnd vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd bga: 1mm pitch, 13mm x 13mm (bc144-1, order code: bc) top view notes: 1. ic - internal connection, tie to ground for normal operation. 2. all i/o pins are 5v tolerant except for tms, tdi and trst .
3 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 tx11 tx10 gnd tx9 tx8 vcc rx15 rx14 rx13 rx12 rx11 rx10 rx9 rx8 gnd tx7 tx6 tx5 tx4 gnd tx3 tx2 tx1 tx0 gnd rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 ic ic ic ic ic ic ic ic gnd oei7 oei6 oei5 oei4 gnd oei3 oei2 oei1 oei0 gnd ic ic ic ic ic ic ic ic tx15 tx14 gnd tx13 tx12 vcc oei8 oei9 gnd oei10 oei11 oei12 oei13 gnd oei14 oei15 d0 d1 gnd d2 d3 d4 d5 gnd d6 d7 vcc d08 d09 gnd d10 d11 vcc d12 d13 gnd d14 d15 dta a13 a12 ic a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a0 r/ w cs ds gnd trst tck tdo tdi tms vcc wfps fe/hclk f0i clk gnd reset ode gnd a1 5903 drw03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc tqfp: 0.50mm pitch, 20mm x 20mm (da144-1, order code: da) top view pin configurations (continued) notes: 1. ic - internal connection, tie to ground for normal operation. 2. all i/o pins are 5v tolerant except for tms, tdi and trst .
4 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 pin description symbol name i/o description gnd ground. ground rail. vcc vcc +3.3 volt power supply. tx0-15 tx output 0 to 15 o serial data output stream. these streams may have a data rate of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s, (three-state outputs) or 16.384 mb/s. oei0-15 output enable o these pins reflect the active or three-state status for the corresponding, (tx0-15) output streams. indication 0 to 15 (three-state outputs) rx0-15 rx input 0 to 15 i serial data input stream. these streams may have a data rate of 2.048 mb/s, 4.096 mb/s, 8.192 mb/s, or 16.384 mb/s. f0i frame pulse i this input accepts and automatically identifies frame synchronization signals formatted according to st-bus ? and gci specifications. fe/hclk frame evaluation/ i when the wfps pin is low, this pin is the frame measurement input. when the wfps pin is high, the hclk hclk clock (4.096 mhz clock) is required for frame alignment in the wide frame pulse (wfp) mode. clk clock i serial clock for shifting data in/out on the serial streams (rx/tx 0-15). tms test mode select i jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an intern al pull-up when not driven. tdi test serial data in i jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an interna l pull-up when not driven. tdo test serial data out o jtag serial data is output on this pin on the falling edge of tck. this pin is held in high-impedance s tate when jtag scan is not enabled. tck test clock i provides the clock to the jtag test logic. trst test reset i asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin is pulled by an internal pull-up when not driven. this pin should be pulsed low on power-up, or held low, to ensure that the idt72v71623 is in the normal functional mode. reset device reset i this input (active low) puts the idt72v71623 in its reset state that clears the device internal counters, register s and brings tx0-15 and microport data outputs to a high-impedance state. in normal operation, the reset pin must be held low for a minimum of 100ns to reset the device. wfps wide frame pulse select i when 1, enables the wide frame pulse (wfp) frame alignment interface. when 0, the device operates in st-bus ? /gci mode. ds data strobe i this active low input works in conjunction with cs to enable the read and write operations. r/ w read/write i this input controls the direction of the data bus lines during a microprocessor access. cs chip select i active low input used by a microprocessor to activate the microprocessor port of idt72v71623. a0-13 address bus 0 to 13 i these pins allow direct access to connection memory, data memory and internal control registers. d0-15 data bus 0-15 i/o these pins are the data bits of the microprocessor port. dta data transfer o this active low signal indicates that a data bus transfer is complete. when the bus cycle ends, this pin drives acknowledgment high and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. a pull-up resistor is required to hold a high level when the pin is in high-impedance. ode output drive enable i this is the output enable control for the tx0-15 serial outputs. when ode input is low and the osb bit o f the ims register is low, tx0-15 are in a high-impedance state. if this input is high, the tx0-15 output drivers are enabled. however, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory.
5 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 description (continued output enable indications are provided through dedicated pins (one pin per output stream) to facilitate external data bus control. the idt72v71623 is capable of switching up to 2,048 x 2,048 channels without blocking. designed to switch 64 kbit/s pcm or n x 64 kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per channel basis. the serial input streams (rx) and serial output streams (tx) of the idt72v71623 can be run up to 16.384 mb/s allowing 256 channels per 125 s frame. depending on the input and output data rates the device can support up to 16 serial streams. with two main operating modes, processor mode and connection mode, the idt72v71623 can easily switch data from incoming serial streams (data memory) or from the controlling microprocessor (connection memory). as control and status information is critical in data transmission, the processor mode is especially useful when there are multiple devices sharing the input and output streams. with two main configuration modes, regular and mux/demux mode the idt72v71623 is designed to work in a mixed data-rate environment. in mux/ demux mode, all of the input streams work at one data rate and the output streams at another. depending on the configuration, more or less serial streams will be available on the inputs or outputs to maintain a non-blocking switch. with data coming from multiple sources and through different paths, data entering the device is often delayed. to handle this problem, the idt72v71623 has a frame evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up to 8 mb/s or +2.5 clock cycles for 16 mb/s. (see table 8 for maximum allowable skew). the idt72v71623 also provides a jtag test access port, an internal loopback feature, memory block programming, a simple microprocessor interface and automatic st-bus ? /gci sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. functional description data and connection memory all data that comes in through the rx inputs go through a serial-to-parallel conversion before being stored into internal data memory. the 8 khz frame pulse (f0i) is used to mark the 125 s frame boundaries and to sequentially address the input channels in data memory. the data memory is only written by the device from the rx streams and can be read from either the tx streams or the microprocessor. data output on the tx streams may come from either the serial input streams (data memory) or from the microprocessor (connection memory). in the case that rx input data is to be output, the addresses in connection memory are used to specify a stream and channel of the input. the connection memory is setup in such a way that each location corresponds to an output channel for each particular stream. in that way, more than one channel can output the same data. in processor mode, the microprocessor writes data to the connection memory locations corresponding to the stream and channel that is to be output. the lower byte (8 least significant bits) of the connection memory is output every frame until the microprocessor changes the data or mode of the channel. by using this processor mode capability, the microprocessor can access input and output time-slots on a per channel basis. the most significant bits of the connection memory are used to control per channel functions such as processor mode, constant or variable delay mode, three-state of output drivers, and the loopback function. operating modes in addition to regular mode where input and output streams are operating at the same rate, the idt72v71623 incorporates a rate matching function, mux/demux mode. in mux/demux mode, all input streams are operating at the same rate, while output streams are operating at a different rate. all configurations are non-blocking. these modes can be entered by setting the dr3-0 bits in the control register, see table 5. output impedance control in order to put all streams in three-state, all per-channel three-state control bits in the connection memory are set (mod0 and mod1 = 1) or both the ode pin and the osb bit of the control register must be zero. if any combination other than 0-0, for the ode pin and the osb bit, is used, the three-state control of the streams will be left to the state of the mod1 and mod0 bits of the connection memory. the idt72v71623 incorporates a memory block programming feature to facilitate three-state control after reset. see table 1 for output high- impedance control. serial data interface timing when a 16mb/s serial data rate is required, the master clock frequency will be running at 16.384mhz resulting in a single-bit per clock. for all other cases, 2mb/s, 4mb/s, and 8mb/s, the master clock frequency will be twice the fastest data rate on the serial streams. use table 5 to determine clock speed and dr3-0 bits in the control register to setup the device. the idt72v71623 provides two different interface timing modes, st-bus ? or gci. the idt72v71623 automatically detects the presence of an input frame pulse and identifies it as either st-bus ? or gci. in st-bus ? , when running at 16.384mhz, data is clocked out on the falling edge and is clocked in on the subsquent rising-edge. at all other data rates, there are two clock cycles per bit and every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of clk, three quarters of the way into the bit cell. see figure 15 for timing. in gci format, when running at 16.384mhz, data is clocked out on the rising edge and is clocked in on the subsquent falling edge. at all other data rates, there are two clock cycles per bit and every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of clk at three quarters of the way into the bit cell. see figure 16 for timing. input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. f0i). although input data is synchronous, delays can be caused by variable path serial backplanes and variable path lengths, which may be implemented in large centralized and distributed switching systems. because data is often delayed this feature is useful in compensating for the skew between clocks. each input stream can have its own delay offset value by programming the frame input offset registers (for, table 7). the frame offset shown is a function of the data rate, and can be as large as +4.5 master clock (clk) periods forward with a resolution of ? clock period. to determine the maximum offset allowed see table 8. serial input frame alignment evaluation the idt72v71623 provides the frame evaluation (fe) input to determine different data input delays with respect to the frame pulse f0i. setting the start frame evaluation (sfe) bit low for at least one frame starts a measurement cycle. when the sfe bit in the control register is changed from low to high, the
6 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 evaluation starts. two frames later, the complete frame evaluation (cfe) bit of the frame alignment register (far) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the far register. the sfe bit must be set to zero before a new measurement cycle is started. in st-bus ? mode, the falling edge of the frame measurement signal (fe) is evaluated against the falling edge of the st-bus ? frame pulse. in gci mode, the rising edge of fe is evaluated against the rising edge of the gci frame pulse. see table 6 and figure 5 for the description of the frame alignment register. memory block programming the idt72v71623 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 15 to 13 of every connection memory location, first program the desired pattern in bits 9 to 7 of the control register. setting the memory block program (mbp) bit of the control register high enables the block programming mode. when the block programming enable (bpe) bit of the control register is set to high, the block programming data will be loaded into the bits 15 to 13 of every connection memory location. the other connection memory bits (bit 12 to bit 0) are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero. loopback control the loopback control (lpbk) bit of each connection memory location allows the tx output data to be looped backed internally to the rx input for diagnostic purposes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., data from txn channel m routes to the rxn channel m internally); if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero and the device must be in regular switch mode (dr3-0 = 0x0, 0x1 or 0x2). delay through the idt72v71623 the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabili- ties on a per-channel basis. for voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the mod1 and mod0 bits of the connection memory. variable delay mode (mod1-0 = 0x0) in this mode, the delay is dependent only on the combination of source and destination serial stream speed. although the minimum delay achievable is dependent on the input and output serial stream speed, if data is switched out +3 channels of the slowest data rate, the data will be switched out in the same frame except if the input and output data rates are both 16 mb/s (dr3-0 = 0x3). (see figure 2 for example). for example, given the input data rate is 2 mb/s and the output data rate is 8 mb/s, input channel ch0 can be switch out by output channel ch12. in the above example the input streams are slower than the output streams. also, for every 2 mb/s time slot there are four 8 mb/s time slots, thus a three 2 mb/s channel delay equates to 12 output channel time slots. see figure 2 for this example and other examples of minimum delay to guarantee transmission in the same frame. constant delay mode (mod1-0 = 0x1) in this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. input channel data is written into the data memory buffers during frame n will be read out during frame n+2. figure 1 shows examples of constant delay mode. microprocessor interface the idt72v71623?s microprocessor interface looks like a standard ram interface to improve integration into a system. with a 14-bit address bus and a 16-bit data bus, read and writes are mapped directly into data and connection memories and require only one master clock cycle to access. by allowing the internal memories to be randomly accessed in one cycle, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. table 2 shows the mapping of the addresses into internal memory blocks, table 3 shows the control register information and figure 11 and figure 12 shows asynchronous and synchronous microprocessor accesses. memory mapping the address bus on the microprocessor interface selects the internal registers and memories of the idt72v71623. the two most significant bits of the address select between the registers, data memory, and connection memory. if a13 and a12 are high, a11-a0 are used to address the data memory (read only). if a13 is high and a12 is low, a11-a0 are used to address connection memory (read/write). if a13 is low and a12 is high a11-a9 are used to select the control register, frame alignment register, and frame offset registers. see table 2 for mappings. control register as explained in the serial data interface timing and switching configura- tions sections, after system power-up, the control register should be pro- grammed immediately to establish the desired switching configuration. the data in the control register consists of the memory block programming bit (mbp), the block programming data (bpd) bits, the begin block program- ming enable (bpe), the output stand by (osb), start frame evaluation (sfe), and data rate select bits (dr 3-0). as explained in the memory block programming section, the bpe begins the programming if the mbp bit is enabled. this allows the entire connection memory block to be programmed with the block programming data bits. connection memory control if the ode pin or the osb bit is high, the mod1-0 bits of each connection memory location controls the output drivers. see table 1 for detail. the processor channel (pc) mode is entered by a 1-0 of the mod1-0 of the connection memory. in processor channel mode, this allows the microproces- sor to access tx output channels. once the mod1-0 bits are set the lower 8 bits of the connection memory will be output on the tx serial streams. also controlled in the connection memory is the variable delay mode or constant delay mode. each connection memory location allows the per-channel selection between variable and constant throughput delay modes and processor mode.
7 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., rxn channel m data comes from the txn channel m). if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero and the device must be in regular switch mode (dr3-0 = 0x0, 0x1 or 0x2). output enable indication the idt72v71623 has dedicated pins to indicate the state of the outputs (active or three-state). see figure 13 for timing. initialization of the idt72v71623 after power up, the idt72v71623 should be reset. during reset, the internal registers are put into their default state and all tx outputs are put into three-state. after reset however, the state of connection memory is unknown. as such, the outputs should be put in high-impedance by holding the ode low. while the ode is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the oe bit in connection memory. once the device is configured, the ode pin (or osb bit depending on initialization) can be switched. see figure 8.
8 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 2 internal register and address memory mapping table 1 output high-impedance control mod1-0 bits in ode pin osb bit in control output driver connection memory register status 1 and 1 don?t care don?t care per channel high-impedance any, other than 1 and 1 0 0 high-impedance any, other than 1 and 1 0 1 enable any, other than 1 and 1 1 0 enable any, other than 1 and 1 1 1 enable a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w location 1 1 sta3 sta2 sta1 sta0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 r data memory 1 0 sta3 sta2 sta1 sta0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 r/w connection memory 0 100 0xxxxx xxxxr/w control register 0 100 1xxxxx xxxxr frame align register 0 101 0xxxxx xxxxr/w for0 0 101 1xxxxx xxxxr/w for1 0 110 0xxxxx xxxxr/w for2 0 110 1xxxxx xxxxr/w for3
9 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 1. constant delay mode examples 1 frame (125 sec) 1 frame (125 sec) 1 frame (125 sec) ? ? ? ? rx 2 mb/s a ? ? ? ? q tx 16 mb/s q (1) ? ? ? ? a (2) dr3-0 = 9 h notes: 1. timeslot q ? 2 frames ? minimum delay. 2. timeslot a ? 3 frames - 1 output channel period ? maximum delay. 1 channel @ 2 mb/s abcdef rx 2 mb/s figure 2. variable delay mode examples tx 8 mb/s rx 16 mb/s tx 8 mb/s a or b (1,2) c or d dr3-0 = 4 h (3) notes: 1. if data is switched at least +3 channel periods of the slower data rate, the data will transmit out in the same frames except if the input and output data rates are both 16 mb/s (dr3-0 = 0x3). 2. delay is a function of input channel and output channel combinations, and input and output stream data rate. 3. see switching mode table for input and output speed combinations. 4. when the input and output data rates are both 16 mb/s, the minimum delay achievable is 6 time slots. 2 mb/s 8 mb/s 1 channel @ 8 mb/s a (1,2) dr3-0 = a h (3) abc def gh i j 1 channel @ 8 mb/s 1 channel @ 16 mb/s 2 mb/s 16 mb/s 16 mb/s 8 mb/s rx 16 mb/s dr3-0 = 3 h (3,4) abcdefgh i jklmno pqr tx 16 mb/s abbba 16 mb/s 16 mb/s
10 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 3 control register (cr) bits table 4 connection memory bits reset value: 4000 h . bit name description 15 reset (software reset) a one will reset the device and have the same effect as of the reset pin. must be zero for normal opera tion. 14 unused must be one for proper operation. 13 oepol when 1, a one on oei pin denotes an active state on the output data stream; zero on oei pin denotes high-impedance state. (output enable polarity) when 0, a one denotes high-impedance and a zero denotes an active state. 12 unused must be zero for normal operation. 11 mbp when 1, the connection memory block programming feature is ready for the programming of connection memory high bits, (memory block program) bit 13 to bit 15. when 0, this feature is disabled. 10 unused must be zero for normal operation. 9-7 bpd2-0 these bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is (block programming data) activated. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the conte nts of the bits bpd2-0 are loaded into bit 15 and 13 of the connection memory. bit 12 to bit 0 of the connection memory are set to 0. 6 bpe a zero to one transition of this bit enables the memory block programming function. the bpe and bpd2-0 bits in the cr regis ter (begin block programming have to be defined in the same write operation. once the bpe bit is set high, the device requires two f rames to complete the enable) block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is comple ted. when the bpe=1, the other bit in the control register must not be changed for two frames to ensure proper operation. 5 osb when ode=0 and osb=0, the output drivers of transmit serial streams are in high-impedance mode. when ode=1 and osb=1, (output stand by) the output serial streams are in high-impedance mode. when ode=1, the output serial stream drivers function no rmally. 4 sfe a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far register changes fr om zero (start frame evaluation) to one, the evaluation procedure stops. to start another frame evaluation cycle, set this bit to zero f or at least one frame. 3-0 dr3-0 input/output data rate selection. see table 5 for detailed programming. 1514131211109876543210 srs 1 oep 0 mbp 0 bpd2 bpd1 bpd0 bpe osb sfe dr3 dr2 dr1 dr0 bit name description 15 lpbk when 1, the rx n channel m data comes from the tx n channel m. for proper per channel loopback operations, set the delay (per channel loopback) offset register bits ofn[2:0] to zero for the streams which are in the loopback mode. this feature is off ered only when dr3-0 = 0000, 0001 or 0010 is selected via the control register. 14,13 mod1-0 mod1 mod0 mode (switching mode selection) 0 0 variable delay mode 0 1 constant delay mode 1 0 processor mode 1 1 output high-impedance 12 unused must be zero for normal operation. 11-8 sab3-0 the binary value is the number of the data stream for the source of the connection. unused sab bits must be zero for prop er (source stream address bits) op eration. 7-0 cab7-0 the binary value is the number of the channel for the source of the connection. unused cab bits must be zero for prope r (source channel address bits) op eration. 1514131211109876543210 lpbk mod1 mod0 0 sab3 sab2 sab1 sab0 cab7 cab6 cab5 cab4 cab3 cab2 cab1 cab0
11 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 3. regular switch mode figure 4. mux/demux mode tx0 tx3 tx4 tx15 5903 drw05 2 mb/s 8 mb/s dr3-0 = 4 h 16 mb/s dr3-0 = 8 h tx0 tx15 2 mb/s open rx4 rx15 rx0 rx3 rx0 rx15 16 mb/s 2 mb/s 2 mb/s 8 mb/s table 5 switch modes switching control bits data rate bits/s clock rate mode dr3 dr2 dr1 dr0 receive streams transmit streams mhz 0 0 0 0 2 m on rx0-15 2 m on tx0-15 4 regular 0 0 0 1 4 m on rx0-15 4 m on tx0-15 8 0 0 1 0 8 m on rx0-15 8 m on tx0-15 16 0 0 1 1 16 m on rx0-7 16 m on tx0-7 16 0 1 0 0 2 m on rx0-15 8 m on tx0-3 16 0 1 0 1 8 m on rx0-3 2 m on tx0-15 16 0 1 1 0 4 m on rx0-15 8 m on tx0-7 16 mux/demux 0 1 1 1 8 m on rx0-7 4 m on tx0-15 16 1 0 0 0 16 m on rx0-1 2 m on tx0-15 16 1 0 0 1 2 m on rx0-15 16 m on tx0-3 16 1 0 1 0 16 m on rx0-7 8 m on tx0-15 16 1 0 1 1 8 m on rx0-15 16 m on tx0-7 16 rx0 rx15 tx0 tx15 5903 drw04 2, 4, 8 mb/s 2, 4, 8 mb/s dr3-0 = 0 h , 1 h , 2 h rx0 rx7 rx8 rx15 16 mb/s dr3-0 = 3 h tx0 tx7 tx8 tx15 16 mb/s open 16 mb/s 16 mb/s 2 mb/s 2 mb/s, 4 mb/s 4 mb/s, 8 mb/s 8 mb/s
12 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 6 frame alignment register (far) bits 0123 456 78 9101112131415 16 st-bus ? frame clk offset value fe input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gci frame clk offset value fe input (fd[10:0] = 06 h ) (fd11 = 0, sample at clk low phase) (fd[10:0] = 09 h ) (fd11 = 1, sample at clk high phase) 5903 drw06 figure 5. example for frame alignment measurement reset value: 0000 h . bit name description 15-13 unused must be zero for normal operation 12 cfe (complete when cfe = 1, the frame evaluation is completed and bits fd10 to fd0 bits contains a valid frame alignment offse t. this bit is reset to frame evaluation) zero, when sfe bit in the cr register is changed from 1 to 0. 11 fd11 the falling edge of fe (or rising edge for gci mode) is sampled during the clk-high phase (fd11 = 1) or during the clk-low phas e (frame delay bit 11) (fd11 = 0). this bit allows the measurement resolution to ? clk cycle. 10-0 fd10-0 the binary value expressed in these bits refers to the measured input offset value. these bits are rest to zero when the sfe bi t of the (frame delay bits) cr register changes from 1 to 0. (fd10 ? msb, fd0 ? lsb) 1514131211109876543210 0 0 0 cfe fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0
13 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 7 frame input offset register (for) bits note: 1. n denotes an input stream number from 0 to 31. reset value: 0000 h for all for registers. 1514131211109876543210 of32 of31 of30 dle3 of22 of21 of20 dle2 of12 of11 of10 dle1 of02 of01 of00 dle0 for0 register 1514131211109876543210 of72 of71 of70 dle7 of62 of61 of60 dle6 of52 of51 of50 dle5 of42 of41 of40 dle4 for1 register 1514131211109876543210 of112 of111 of110 dle11 of102 of101 of100 dle10 of92 of91 of90 dle9 of82 of81 of80 dle8 for2 register 1514131211109876543210 of312 of311 of310 dle31 of142 of141 of140 dle14 of132 of131 of130 dle13 of122 of121 of120 dle12 for3 register name (1) description ofn2, ofn1, ofn0 these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the rx i nput pin: i.e., to start a new frame. (offset bits 2, 1 & 0) the input frame offset can be selected to +4.5 clock periods from the point where the external frame puls e input signal is applied to the f0i input of the device. see figure 6. dlen st-bus ? mode: dlen = 0, if clock rising edge is at the ? point of the bit cell. (data latch edge) dlen = 1, if when clock falling edge is at the ? of the bit cell. gci mode: dlen = 0, if clock falling edge is at the ? point of the bit cell. dlen = 1, if when clock rising edge is at the ? of the bit cell.
14 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 8 maximum allowable skew switching control bits data rate bits/s maximum mode dr3 dr2 dr1 dr0 receive streams transmit streams allowable skew 0 0 0 0 2 m on rx0-15 2 m on tx0-15 +4.5 regular 0 0 0 1 4 m on rx0-15 4 m on tx0-15 +4.5 0 0 1 0 8 m on rx0-15 8 m on tx0-15 +4.5 0 0 1 1 16 m on rx0-7 16 m on tx0-7 +2.5 0 1 0 0 2 m on rx0-15 8 m on tx0-3 +1.5 0 1 0 1 8 m on rx0-3 2 m on tx0-15 +4.5 0 1 1 0 4 m on rx0-15 8 m on tx0-7 +1.5 mux/demux 0 1 1 1 8 m on rx0-7 4 m on tx0-15 +4.5 1 0 0 0 16 m on rx0-3 2 m on tx0-15 +2.5 1 0 0 1 2 m on rx0-15 16 m on tx0-3 +1.5 1 0 1 0 16 m on rx0-7 8 m on tx0-15 +4.5 1 0 1 1 8 m on rx0-15 16 m on tx0-7 +4.5
15 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 6. examples for input offset delay timing in 16 mb/s mode st-bus ? f0i rx stream (16.384 mb/s) 5903 drw07 bit 7 bit 7 16.384 mhz clk bit 6 offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 gci f0i bit 0 bit 0 offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 bit 1 bit 0 bit 2 bit 1 bit 2 bit 1 bit 2 rx stream (16.384 mb/s) 16.384 mhz clk rx stream (16.384 mb/s) rx stream (16.384 mb/s) bit 6 bit 5 bit 4 bit 5 bit 6 bit 7 bit 5 bit 4 rx stream (16.384 mb/s) rx stream (16.384 mb/s) note: 1. see table 8 for maximum allowable offsets. table 9 offset bits (ofn2, ofn1, ofn0, dlen) & frame delay bits (fd11, fd2-0) measurement result from corresponding input stream frame delay bits offset bits offset fd11 fd2 fd1 fd0 ofn2 ofn1 ofn0 dlen no clock period shift (default) 10000000 + 0.5 clock period shift 00000001 + 1.0 clock period shift 10010010 + 1.5 clock period shift 00010011 + 2.0 clock period shift 10100100 + 2.5 clock period shift 00100101 + 3.0 clock period shift 10110110 + 3.5 clock period shift 00110111 + 4.0 clock period shift 11001000 + 4.5 clock period shift 01001001
16 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 6. examples for input offset delay timing in 8 mb/s, 4 mb/s and 2 mb/s mode (continued) st-bus ? f0i rx stream 5903 drw08 bit 7 bit 7 clk bit 7 bit 7 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 gci f0i bit 0 bit 0 clk bit 0 bit 0 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 rx stream rx stream rx stream rx stream rx stream rx stream rx stream
17 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 jtag support the idt72v71623 jtag interface conforms to the boundary-scan stan- dard ieee-1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. test access port (tap) the test access port (tap) provides access to the test functions of the idt72v71623. it consists of three input pins and one output pin. test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remain independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to v cc when it is not driven from an external source. test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v cc when it is not driven from an external source. test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high-impedance state. test reset ( trst ) reset the jtag scan structure. this pin is internally pulled to v cc . instruction register in accordance with the ieee-1149.1 standard, the idt72v71623 uses public instructions. the idt72v71623 jtag interface contains a two-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. value instruction 00 extest 11 bypass 01 or 10 sample/preload test data register as specified in ieee-1149.1, the idt72v71623 jtag interface contains two test data registers: the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the idt72v71623 core logic. the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. the idt72v71623 boundary scan register bits are shown in table 10. bit 0 is the first bit clocked out. all three-state enable bits are active high. jtag instruction register decoding
18 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 table 10 boundary scan register bits boundry scan bit 0 to bit 168 device pin three-state output input control scan cell scan cell ic 93 ic 94 ic 95 ic 96 oei7 97 98 oei6 99 100 oei5 101 102 oei4 103 104 oei3 105 106 oei2 107 108 oei1 109 110 oei0 111 112 ic 113 ic 114 ic 115 ic 116 ic 117 ic 118 ic 119 ic 120 tx15 121 122 tx14 123 124 tx13 125 126 tx12 127 128 tx11 129 130 tx10 131 132 tx9 133 134 tx8 135 136 rx15 137 rx14 138 rx13 139 rx12 140 rx11 141 rx10 142 rx9 143 rx8 144 tx7 145 146 tx6 147 148 tx5 149 150 tx4 151 152 tx3 153 154 tx2 155 156 tx1 157 158 tx0 159 160 rx7 161 rx6 162 rx5 163 rx4 164 rx3 165 rx2 166 rx1 167 rx0 168 boundary scan bit 0 to bit 168 device pin three-state output input control scan cell scan cell ode 0 reset 1 clk 2 f0i 3 fe/hclk 4 wfps 5 ds 6 cs 7 r/ w 8 a0 9 a1 10 a2 11 a3 12 a4 13 a5 14 a6 15 a7 16 a8 17 a9 18 a10 19 a11 20 ic 21 a12 22 a13 23 dta 24 d15 25 26 27 d14 28 29 30 d13 31 32 33 d12 34 35 36 d11 37 38 39 d10 40 41 42 d9 43 44 45 d8 46 47 48 d7 49 50 51 d6 52 53 54 d5 55 56 57 d4 58 59 60 d3 61 62 63 d2 64 65 66 d1 67 68 69 d0 70 71 72 oei15 73 74 oei14 75 76 oei13 77 78 oei12 79 80 oei11 81 82 oei10 83 84 oei9 85 86 oei8 87 88 ic 89 ic 90 ic 91 ic 92
19 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 symbol parameter min. typ. max. units i cc (2) supply current - - 75 ma i il (3,4) input leakage (input pins) - - 60 a i oz (3,4) high-impedance leakage - - 60 a v oh (5) output high voltage 2.4 - - v v ol (6) output low voltage - - 0.4 v symbol rating level unit v tt ttl threshold 1.5 v v hm ttl rise/fall threshold voltage high 2.0 v v lm ttl rise/fall threshold voltage low 0.8 v dc electrical characteristics ac electrical characteristics - timing parameter measurement voltage levels notes: 1. voltages are with respect to ground (gnd) unless otherwise stated. 2. outputs unloaded. 3. 0 v v cc . 4. maximum leakage on pins (output or i/o pins in high-impedance state) is over an applied voltage (v). 5. ioh = 10 ma. 6. iol = 10 ma. s1 is open circuit except when testing output levels or high-impedance states. s2 is switched to v cc or gnd when testing output levels or high-impedance states. figure 7. output load symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v vi voltage on digital inputs gnd -0.3 5.3 v i o current at digital outputs -50 50 ma t s storage temperature -55 +125 c p d package power dissapation ? 2w note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. absolute maximum ratings (1) recommended operating conditions (1) note: 1. voltages are with respect to ground unless otherwise stated. symbol parameter min. typ. max. unit v cc positive supply 3.0 3.3 3.6 v v ih input high voltage 2.0 ? 5.3 v v il input low voltage ?? 0.8 v t op operating temperature -40 25 +85 c commercial test point output pin c l gnd s 1 r l vcc gnd 5903 drw09 s 2
20 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 ac electrical characteristics - frame pulse and clk symbol parameter min. typ. max. units t fpw (1) frame pulse width (st-bus ? , gci) bit rate = 2.048 mb/s 26 ? 295 ns bit rate = 4.096 mb/s 26 ? 145 ns bit rate = 8.192 mb/s or 16.384 mb/s 26 ? 65 ns t fps (1) frame pulse setup time before clk falling (st-bus ? or gci) 5 ?? ns t fph (1) frame pulse hold time from clk falling (st-bus ? or gci) 10 ?? ns t cp (1) clk period bit rate = 2.048 mb/s 190 ? 300 ns bit rate = 4.096 mb/s 110 ? 150 ns bit rate = 8.192 mb/s or 16.384 mb/s 58 ? 70 ns t ch (1) clk pulse width high bit rate = 2.048 mb/s 85 ? 150 ns bit rate = 4.096 mb/s 50 ? 75 ns bit rate = 8.192 mb/s or 16.384 mb/s 20 ? 40 ns t cl (1) clk pulse width low bit rate = 2.048 mb/s 85 ? 150 ns bit rate = 4.096 mb/s 50 ? 75 ns bit rate = 8.192 mb/s or 16.384 mb/s 20 ? 40 ns t r , t f clock rise/fall time ?? 10 ns t hfpw (2) wide frame pulse width hclk = 4.096 mhz 244 ns hclk = 8.192 mhz 122 ns t hfps (2) frame pulse setup time before hclk 4 mhz falling 50 ? 150 ns t hfph (2) frame pulse hold time from hclk 4 mhz falling 50 ? 150 ns t hfps (2) frame pulse setup time before hclk 8 mhz rising 45 ? 90 ns t hfph (2) frame pulse hold time from hclk 8 mhz rising 45 ? 90 ns t hcp (2) hclk period @ 4.096 mhz 244 ns @ 8.192 mhz 122 ns t hr , t hf hclk rise/fall time ?? 10 ns t dif (3) delay between falling edge of hclk and falling edge of clk -10 ? 10 ns notes: 1. wfps pin = 0. 2. wfps pin = 1. 3. wfps pin = 0 or 1.
21 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 8. reset and ode timing reset tx ode t rs t zr t rz t rz t ode 5903 drw10 figure 9. serial output and external control figure 10. output driver enable (ode) clk (st-bus ? or wfps mode) tx tx valid data valid data t zd clk (gci mode) 5903 drw11 t dz ode tx valid data 5903 drw12 t ode t ode
22 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 ac electrical characteristics - microprocessor interface timing notes : 1. c l = 150pf 2. r l = 1k 3. high-impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 4. to achieve one clock cycle fast memory access, this setup time, t dss should be met. otherwise, worst case memory access operation is determined by t akd . symbol parameter min. typ. max. units t css cs setup from ds falling 0 ?? ns t rws r/w setup from ds falling 3 ?? ns t ads address setup from ds falling 2 ?? ns t csh cs hold after ds rising 0 ?? ns t rwh r/w hold after ds rising 3 ?? ns t adh address hold after ds rising 2 ?? ns t ddr (1) data setup from dta low on read 2 ?? ns t dhr (1,2,3) data hold on read 10 15 25 ns t dsw data setup on write (register write) 10 ?? ns t swd valid data delay on write (connection memory write) - ? 0ns t dhw data hold on write 5 ?? ns t dspw ds pulse width 5 ?? ns t ckak clock to ack ?? 35 ns t akd (1) acknowledgment delay: reading/writing registers 30 ns reading/writing memory @ 2.048 mb/s 345 ns @ 4.096 mb/s 200 ns @ 8.192 mb/s or 16.384 mb/s 120 ns t akh (1,2,3) acknowledgment hold time ?? 15 ns t dss (4) data strobe setup time 2 ?? ns
23 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 11. asyncronous bus timing figure 12. syncronous bus timing ds cs valid write address a0-a13 t css t csh r/ w t rws t rwh t ads t adh valid write data d0-d15 t dsw t dhw dta t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 5903 drw13 5903 drw14 d0-d15 cs dta valid write address r/ w a0-a13 ds clk gci clk st-bus ? t dss t css t csh t rws t rwh valid read address t ads t adh valid read data t dhr t ckak t akh t ddr t dspw t dss t css t csh t rws t rwh t ads t adh valid write data t swd t dhw t ckak t akh
24 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 13. output enable indicator timing (8 mb/s st-bus ? ) t cp t ch t cl t r t f t fpw t fph t fps f0i clk 16.384 mhz 5903 drw15 bit 5 bit 6 bit 7 bit 4 t sod bit 1 bit 2 bit 3 bit 0 t zd tx 8 mb/s t oeie t oeie oei (1) t oeid t oeid t dz oei (2) notes : 1. when oepol = 1, oei is high when tx is active and low when tx is in three-state. 2. when oepol = 0, oei is low when tx is active and high when tx is in three-state.
25 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 figure 14. wfps timing t cp t ch t r t f t cl t hch t hcl t hf t hr bit 0 bit 7 bit 6 bit 5 bit 4 t sis bit 3 bit 2 bit 1 bit 0 t sih rx 8 mb/s bit 1 5903 drw16 rx 16 mb/s bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 2 bit 1 t sih t sis bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 t sod tx 16 mb/s bit 2 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hclk- 4.096 mhz tx 8 mb/s t dif t hf t hr hclk- 8.192 mhz t dif clk- 16.384 mhz t hfph f0i t hfps t hfpw bit 1 t sod t hcl t hch t hcp t hcp
26 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 symbol parameter min. typ. max. units t sis rx setup time 2 ?? ns t sih rx hold time 10 ?? ns t sod tx delay ? active to active ?? 22 ns t dz (1) tx delay ? active to high-z ?? 22 ns t zd (1) tx delay ? high-z to active ?? 22 ns t ode (1) output driver enable (ode) delay ?? 30 ns t oeie output enable indicator (oei) enable ?? 40 ns t oeid output enable indicator (oei) disable ?? 25 ns t rz active to high-z on master reset ?? 30 ns t zr high-z to active on master reset ?? 30 ns t rs reset pulse width 100 ?? ns ac electrical characteristics (1) ? serial stream (st-bus ? and gci) note: 1. high-impedance is measured by pulling to the appropriate rail with r l (1k ? ), with timing corrected to cancel time taken to discharge c l (150 pf).
27 commercial temperature range idt72v71623 3.3v time slot interchange digital switch 2,048 x 2,048 t sis t sih 5903 drw17 tx 8 mb/s rx 8 mb/s tx 4 mb/s rx 4 mb/s bit 7 t sod bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 t sod bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 t sis t sih bit 7 bit 6 bit 5 bit 4 bit 0 tx 2 mb/s rx 2 mb/s t sod bit 7 bit 0 bit 6 bit 5 t sis t sih bit 7 bit 6 bit 0 bit 1 bit 0 t fpw t fph t fps f0i clk- 16.384 mhz tx 16 mb/s rx 16 mb/s bit 7 bit 0 t sis t sih bit 7 t sod bit 1 bit 2 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 0 bit 1 bit 2 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 t cp t ch t cl t r t f figure 15. st-bus ? timing figure 16. gci timing t sis t sih bit 7 bit 6 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 t sis t sih bit 0 bit 1 bit 2 bit 3 bit 7 5903 drw18 bit 0 bit 1 bit 7 t sis t sih tx 8 mb/s rx 8 mb/s tx 4 mb/s rx 4 mb/s bit 0 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 6 t sod bit 0 bit 7 bit 1 bit 2 bit 3 t sod bit 0 bit 7 bit 1 t sod tx 2 mb/s rx 2 mb/s tx 16 mb/s rx 16 mb/s t fpw t fph t cp t r t f t fps t ch t cl f0i clk- 16.384 mhz t sis t sih bit 0 bit 0 t sod bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 bit 6 bit 5 bit 4 bit 1 bit 0 bit 7 bit 4 bit 3 bit 2 bit 7 bit 6 bit 5 bit 7 bit 6 bit 3 bit 2 bit 1 bit 6 bit 5 bit 4 bit 1 bit 0 bit 7 bit 4 bit 3 bit 2 bit 7 bit 6 bit 5
28 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com 5903 drw19 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 72v71623 2,048 x 2,048 ? 3.3v time slot interchange digital switch with rate matching bc da ball grid array (bga, bc144-1) thin quad flatpacks (tqfp, da144-1) ordering information datasheet document history 5/01/2000 pg. 1 6/07/2000 pgs. 3 and 4. 10/10/2000 pgs. 1 through 28. 11/20/2000 pgs. 10 and 11. 03/09/2001 pg. 19 08/20/2001 pg. 22. 10/22/2001 pg. 1. 1/04/2002 pgs. 1 and 19. 05/17/2002 pg. 26

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